1. Field of the Invention
The present invention relates generally to digital memory devices and, more particularly, to semiconductor memory devices that store and retrieve data from memory cells according to a fixed data burst order.
2. Description of the Related Art
A digital memory, such as a dynamic random access memory (DRAM) has a memory array consisting of a number of individual m-bits or memory cells. Each working cell is adapted to store one binary digit (bit) of data. In a conventional DRAM device each memory cell consists of one transistor and one capacitor. A terminal of the transistor is connected to a column line (or digit line) of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a row line of the memory device. The transistor acts as a gate between the column line and the capacitor. When data is read from the cell, the terminal of the capacitor is electrically connected to the column line and the charge state of the capacitor affects the voltage on the column line, thereby indicating the stored logical value for readout.
In many integrated circuit memory applications, the time required for data retrieval is an important design consideration. The ability to consistently and rapidly retrieve stored data is of immediate technical and commercial value. Accordingly, rapid data retrieval is very desirable, and many efforts have been made to reduce access times. These efforts have addressed device design, manufacturing processes, and integrated circuit system architectures.
In a memory integrated circuit, a select signal must be communicated from an address decoder to a memory cell within a memory array. Thereafter, data to be output must be communicated from the memory cell to an output buffer that drives an output connection of the circuit. As would be understood by one of ordinary skill in the art, communicating a select signal assumes that a row has been opened and, includes triggering sense amplifiers, activating a DQ, and selecting a column. Connecting pathways between an accessed memory cell and an output buffer generally include a sense amplifier, a digit line trace that connects a cell to the sense amplifier, an I/O line trace that connects the sense amplifier to a mux/demux, and a further I/O line trace that connects the mux/demux to the output buffer. Typically, the data transfer is initiated synchronously with transitions of a clock signal. The data is provided from the memory cell in the form of electrical data signals transferred along conductive column lines and I/O traces to an output buffer. Typically, the data is output from the output buffer synchronously with a further transition of the clock signal. Generally, the data signal to be output must have traversed the device and stabilized at the output buffer prior to the further transition of the clock signal. Otherwise, there is a risk that the value output from the buffer will not properly reflect the data value stored in the memory cell. Therefore, digital memory devices are limited in speed by the time taken for signals to traverse the device from an address decoder to a memory cell, and from the memory cell to an output buffer. While this delay is small in human terms, it is significant in the context of many systems in which memory integrated circuits are applied. There is, therefore, a need to reduce the detrimental effect of this delay.
Improvements in memory speed have been achieved by various data retrieval schemes. One such scheme is embodied in a double data rate random access memory that exemplifies a second order (or 2N) prefetch memory architecture.
In a first order (1N) memory architecture integrated circuit device, a read signal is followed by an output of data. The output of data typically consists of a bit or a plurality of parallel bits on respective data paths. The recovered data is all put out on an attached data bus at the same time. Thereafter, no additional data is output until a further read signal requests additional data.
In an architecture of order greater than one (e.g., 2N, 4N, etc.), a read signal is followed a data burst on each data path. The data burst includes two or more data bits (e.g., 2N=2 data bits, 4N=4 data bits, etc.), which are output in sequence. Unlike a first order system, more than one successive data output occurs between consecutive read request signals.
Physical read latency denotes the finite amount of time required for data to be retrieved from an array location following a read column access. This delay is due to the physical constraints of the circuit. For example the RC time constant associated with the row line between the row address decoder and a particular memory cell determines transit time through the row line. Similarly, the RC time constants of lines between the addressed memory cell and the output buffer contribute to read latency. Typically, physical read latency is on the order of 15-20 ns.
The clock cycle latency of a system denotes a rule that requires that the first bit of data from a read access will be available at the output of the device a specified number of clock cycles after a read request is made. For example, for a device with the physical read latency of 20 ns, a clock latency (rule) of 2.5 requires that the clock signal have a maximum frequency of 125 MHz (20 ns/2.5 clock cycles=8 ns/clock cycle: yields a frequency of 125 MHz). In a further example, for a device with a 20 ns physical read latency, and a clock cycle latency of 2, the maximum clock frequency for reliable operation is 100 MHz.
In a conventional device, the slowest bit in the array (i.e. the bit exhibiting the highest physical read latency) determines the maximum permissible operating frequency of the device clock signal for a given value of clock cycle latency, or the number of clock cycles required before read data can be output.
The magnitude of the physical read latency of a particular memory cell depends on several factors, including RC time constants, the spatial length of the conductors connecting the address decoder to the memory cell and the spatial length of the conductors connecting the cell to the device output. Together, these factors make up what is called the electrical length traveled by the access and data signals during a data read.